Leakage current & current leaks – part 3

This post will focus on “current leaks”, the points of power consumption that are often designed into a device without much thought. In some cases they are things you have some amount of control over, in other cases they are things you have little control over but have to account for in your power budget in order to get an accurate power consumption or battery life estimate. While technically not leaks as in leakage current, I call them leaks because they are where your battery life drains away.

Resistive leaks

The amount of power a pull-up resistor consumes surprises most engineers new to low power design. At 10K ohms, a pull-up to 3.3V on a single low level input to a micro can draw over 300uA. Even a fairly high value like 1Meg ohm can draw over 3uA in the same situation. This may seem low but can be considerable compared to a micro with sub-microamp sleep current or a power budget of several microamps average current to achieve several year life from a coin cell battery. The internal pull-up/down resistors on a micro’s GPIO are usually not well controlled and typically range from 5K to 20K ohms. They should never be used if you are concerned with low power consumption.

In situations like open-collector or tri-state outputs a pull-up or pull-down resistor is required (and depending on signal rise-time requirements a fairly low value may be required). In this case the power just needs to be accounted for in the power budget. In other cases, you may have other options. For example, for a switch that only connects to the micro’s inputs and does not directly connect to a hardware circuit, consider the following:

  • Instead of grounding one side of a SPST switch with a pull-up on the micro’s side, use a GPIO instead of ground. This GPIO can be set normally high and then only set low when the micro needs to “read” the switch input. This output from the micro can be shared with several switches. There will still be a small current flow when the switch is closed since the GPIO may only reach 70%-90% of the Vcc rail. To reduce the current flow even more, when not needed enable the internal pull-up for this GPIO and configure it as an input.
  • Use a SPDT switch with one side pulled-up and the other tied to ground. In this setup a pull-up isn’t required on the micro’s input (be sure to select a switch that doesn’t have an “open” position). A SPDT switch is usually larger and more expensive than a SPST switch but the current savings can be significant.

Voltage dividers can be another source of wasted power. When used in a circuit there is little you can do about them other than using the highest value resistors your circuit can tolerate (and accounting for them in your power budget). When used to reduce a voltage for an A/D converter input, a P-FET can be used to turn off the voltage at the top of the divider until the firmware is ready to read the voltage level (the bottom resistor will act as a pull-down to prevent the A/D input from floating). A small amount of current will flow through the P-FET when turned off but it should be much lower than the current through the divider if the P-FET is not used.  In this situation, an N-FET can not be used at the bottom of the divider since when it is turned off the A/D converter input may exceed its input voltage spec.

A thermistor circuit is essentially a voltage divider with one resistor whose value varies with temperature. When using a thermistor with an A/D converter, depending on the voltage rail used for the high side of the thermistor, a P-FET may be used here too or a lower cost N-FET can be used at the bottom the divider. If super accurate temperature measurements are not important, a GPIO can be connected to the top or bottom of the divider. If doing this, it is better to use the GPIO at the bottom since there is usually less variation in the low level output (0.2V to 0.4V for most micros) than for the high level output (70% to 90% of Vcc) so the temperature measurements will be more accurate, however this will consume more power in the “off” state than if you use the GPIO at the top. You can also take the GPIO to an A/D input to and use the actual voltage to adjust the thermistor reading for improved accuracy.

Termination resistors for a serial communications interface are another sneaky path for leaking current. The two signal I2C interface is commonly used for connecting memory, A/D converters and various types of sensors to a micro. Over short distances, the value of the pull-up resistors on these two lines is determined mainly by the maximum transfer speed required on the interface along with the input leakage current of the devices attached to the interface. If I2C communications are part of the normal operation of your device you should work through the exercise of sizing the pull-up resistors and not just rely on values you saw on a reference design. Properly sizing the resistors will ensure the least amount of current is lost through these resistors and provide the information you need to budget for this current draw.

RS485 is another good example of a serial interface with terminating resistors. RS485 is often used in industrial environments and uses a differential pair for transferring data. In a point to point setup, there is typically a 100 or 120 ohm resistor placed across the pair. When the interface is in the idle state, 1.6mA or 2mA flows through this resistor. Since the two differential lines are always in opposite states during a data transfer, at the 1.5V minimum differential voltage 12.5mA or 15mA will flow through the resistor during data transfers. In a multi-drop configuration bias resistors are incorporated, a pull-up to 5V on one of the lines and a pull-down to ground on the other line. These resistors are usually in the 680 ohm to 1K ohm range. With a 1K ohm pull-up, a 1K pull-down and a 120 ohm resistor across the pair, about 2.4mA will flow through these resistors at all times.

Termination resistors make wired Ethernet a real power hog. Depending on the speed and configuration, the two termination resistors on the differential output driver alone can draw upwards of 60mA CONTINOUSLY.  Also, transmit currents can easily run in the 100mA to 180mA range for an Ethernet controller. Don’t think your device will only be transmitting when it has data to send. This could make for another series of blog posts but the protocol being used on the network can generate a significant amount of network traffic that your application is completely unaware of. It seems like for a wired Ethernet connected device, the only practical alternatives to line-power would be Power-over-Ethernet or a good sized solar panel and lead-acid battery unless the Ethernet interface is kept powered down except when the device needs to transmit (and the protocol selected/tweaked to handle that).

Enables and chip selects

In an analog signal chain feeding into an A/D converter for periodic sampling, using an op-amp with an enable can save milliamps compared to an op-amp that is operating all the time. The short time penalty paid in allowing the signal to settle after enabling the op-amp before performing the A/D conversion needs to be taken into consideration. Even if the settling time extends into a few milliseconds, the micro should be able to wake up, enable the op-amp and then go back to sleep while waiting for the settling period.

It may be tempting when using a part like an EEPROM with a SPI interface to tie the chip select pin low to save a GPIO for some other purpose when there are no other devices on the SPI interface. This is a bad idea if you are concerned about low power consumption. On many devices the chip select also serves to put the device into either active mode or standby mode so always having the chip select active will prevent the device from entering standby mode. In reviewing a few small EEPROM datasheets (256 x 8 parts), the active read currents were in the 1mA to 3mA range while the standby currents were in the 1uA to 5uA range (with the CS pin specifically called out at Vcc). This bears further research and experimentation to see what the current draw would be with CS active while the SPI lines are in an idle state but it is likely to be closer to the read current than the standby current. As an aside, some parts may not even function with the chip select always active.  Some devices require a transition on the CS line to enter an active state and for some the CS pin can serve multiple functions, such as starting a conversion on an A/D converter.

For the ultimate power savings with a device like a serial EEPROM or Flash device, if the part isn’t frequently used then use a GPIO and a P-FET to control power to the FET. Some micro manufacturers have design notes showing an EEPROM being powered directly by a high-current GPIO. This may not work reliably depending on several specs of the micro and the EEPROM. As mentioned earlier, the high level output for a CMOS device is typically spec’d at 70% to 90% of Vcc. If the EEPROM is being powered at 70% of the micro’s Vcc rail (2.31V for a 3.3V Vcc) that may be below the EEPROM’s operating voltage. If that is not an issue, if the EEPROM output is at 70% its Vcc rail (1.6V if Vcc is at 2.3V) it likely will not reach the minimum high level input voltage for the micro. If that isn’t a problem, when turned off the EEPROM’s Vcc pin may still be at 0.2V to 0.4V (the maximum low level output voltage) so the EEPROM may draw more current than it normally would in standby. Using a P-FET to control power to the EEPROM addresses all of these potential issues.

If you decide to control power to an EEPROM, Flash or any other device, be sure to consider:

  • Any pull-up resistors used on signals connected to the device powered down must be tied to the Vcc rail of the device, not the micro or considerable current may flow through the pull-up when the device is turned off. Otherwise, if the pull-up value is low enough the device may even remain powered up and if an internal GPIO pull-up is used enough current may flow to damage the micro.
  • Inputs to the micro from the powered down circuit should have pull-down resistors to prevent the signals from floating or the GPIO reconfigured as an output driving a low when the device is off.
  • If using a bypass cap on the device, it will be charged and discharged every time the device is turned on so use as small a value cap as possible. This will minimize power wasted in charging the cap and allow the device Vcc rail to fall quickly and minimize any unexpected behavior as the device powers down.

If you are concerned about ultra-low power consumption and need a device with a SPI or I2C interface, take the time to research the standby currents for similar devices with each interface. I did this with two EEPROMs from the same manufacturer with nearly identical specifications except for the interface. The standby current for the SPI device across its voltage range was 0.5uA to 3.5uA while the range for the I2C device was 1uA to 6uA. Presumably the difference is due to the additional circuitry required to monitor the I2C interface for activity and transition between standby and active modes. This may not seem like a significant difference but it would make literally years of difference in operational life when using a coin cell battery.

Voltage regulators

Voltage regulator circuits can use and waste considerable amounts of power. The current draw of the voltage regulator IC itself can be substantial and easily overlooked while concentrating on efficiency numbers or drop-out voltage specs. For LDOs, look for the “ground pin current” spec which typically increases with the load current and can vary from tens of microamps to tens of milliamps. For switching regulators, look for the “operating current” or “quiescent current” spec. This typically increases with the switching frequency and ranges from hundreds of microamps to a few milliamps.

Switching voltage regulators although generally more efficient than linear regulators can also waste power through poor selection of topologies and components.  This wasted power is hard to “see” in a circuit and can be hard to uncover without comparing the power into the regulator and power out of the regulator. I won’t get into a full discussion of the regulator circuits and topologies but here are a few things to consider:

  • An integrated regulator chip is typically smaller and cheaper than a controller chip and external devices but generally are not as efficient as a well designed regulator circuit. Having said that, if you don’t have much experience with regulator circuits and don’t have time to thoroughly research them, an integrated regulator chip will likely provide a more efficient solution.
  • A synchronous rectifier circuit will generally improve efficiency over a comparable non-synchronous circuit by several percentage points.  However, as the circuit’s duty cycle increases the difference in efficiency tends to decrease. Duty cycle typically increases as the difference between voltage-in and voltage-out decreases so with a low voltage differential (say 5V to 3.3V) synchronous rectification has less benefit.  For relatively low power circuits there won’t be a significant cost or size difference between the two circuits.
  • It can be tempting to pick regulators with very high switching frequencies in order to use smaller inductors and capacitors. As the switching frequency increases the amount of power used in turning the MOSFET(s) on also increases and can become a significant part of the power dissipation of the regulator circuit. If a high switching frequency is required, look for a MOSFET with low gate charge or gate capacitance specs.
  • As mentioned in Part 2, the efficiency of a MOSFET is a function of gate voltage and load current. Most smallish N-channel FETs need a gate voltage in the 8-10V range to fully turn on so if stepping down from 5V the FET will never completely turn-on and the actual RDS(on) may be several times higher than the datasheet spec. There are a number of newer N-FETs that are optimized for low voltage operation and will perform better with a low input voltage and relatively low currents.
  • Before selecting a switching regulator over an LDO for battery powered application, be sure to consider the minimum voltage in/out differential of the switching regulator. Where an LDO may only require a 100mV differential a switching regulator may require 500mV or more. Depending on the battery technology and discharge curve, that high of a voltage differential could reduce the effective battery capacity by 10% to 20% or much more.

Temperature & current leaks

It has been touched on a couple of times through this series of posts but bears repeating, hot temperatures can negatively impact a device’s power consumption. This may be due to increased leakage current or increased RDS(on) of the FET(s) in a regulator circuit. For an ultra-low power design it is critical that you pay attention to the thermal aspect of your design to get as much heat out of the packages as practical, poor thermal design will contribute to your current leaks. Particularly in small SMT packages, for a specific device offered in a variety of packages the thermal resistance can vary by a factor of 10X or more from package to package. The encapsulation materials used for most SMT parts are very poor thermal conductors so in general, the fewer pins a part has and the smaller the pins are the worse its thermal performance will be. Leadless packages that solder directly to the PCB tend to have much better thermal characteristics than leaded packages that must conduct heat through their pins.

It is important to really understand the thermal resistance specifications in a device’s datasheet. If there is no airflow inside your product the basic junction-to-ambient thermal resistance spec is of little use.  With no airflow the majority of the heat dissipation will occur through the circuit board, making the junction-to-board or junction-to-case thermal resistance the spec of interest. With SMT packages used for power devices (particularly packages with a thermal pad) the junction-to-case spec usually refers to the bottom of the case but that isn’t always the true, it may refer to the top of the case.  Particularly when comparing thermal resistance specs from different manufacturers it is important to understand what each spec really means to know if a comparison is valid or not.

That wraps up this series of posts on leakage currents and current leaks.  These are all areas that must be considered for successful low power design.  As you should have noticed, missing just one of these points of leakage current or current leaks can blow away your entire power budget and the lower your power budget is the more critical all of them become.