Tag Archives: leakage current

Keep it cool

Several of my recent posts have mentioned the very negative impact of heat on power consumption. This is the first of a two part series of posts on thermal management for low power devices. This information is mostly taken from my “Low Power Design” PDF e-book.

As semiconductor geometries have shrunk, in recent years leakage current has become a significant component of the overall power consumed by ICs. As parts heat up, their leakage current typically increases. It is not uncommon for parts to consume twice as much current at their highest rate temperature than at their lowest. For example, the AD8226 op-amp is rated for -40°C to 125°C. The quiescent current ranges from 325uA at -40°C to 425uA at 25°C to 600uA at 125°C. This is nearly a 100% increase across the temperature span and nearly a 50% increase from “room temperature” to the maximum temperature. You should conduct your current measurements at the temperature your product will normally operate at if not at the temperature extremes too.

 Controlling Heat

Even if you don’t have the luxury of airflow in your product, there are a number of things you can do to keep the heat under control and reduce the impact of heat on your power consumption:

  • If your product is vertically mounted, place as much circuitry as you can below the main heat generating parts.
  • If you have the option for voltage regulators and other heat generating parts, select packages with bottom side ground or thermal pads. Dissipating heat into the circuit board can help localize the heat buildup and maintain a lower air temperature within the enclosure.
  • For products that operate in high temperatures and have more than a few ICs, select part packages based on what you want to do thermally for a part. For parts that drive large loads or use high clock speeds it can be beneficial to select a package with a low thermal resistance to help get the heat away from the die. On the other hand, if you must place other parts near heat sources on your board you can choose a package with a higher thermal resistance for those other parts to reduce the heat transferred from the PCB to the die. Most surface mount ICs have several options for package styles that can have a wide range of thermal resistances. For instance, Texas Instruments offers the 74LV74 in 6 different packages with thermal impedances ranging from 47°C/W to 127°C/W.
  • Without forced air flow in your product, the junction-to-ambient thermal resistance spec probably isn’t relevant for selecting parts. You need to pay attention to the junction-to-case thermal resistance specs. Some manufacturers are specifying a junction-to-board thermal resistance which is even better. When comparing the junction-to-case thermal resistance of different packages you must understand where on the case this spec applies. Newer parts and particularly those in SMT packages intended for power applications will use the bottom of the case for this spec while older parts and non-power packages will likely use the top of the case since the assumption is air flow is used to dissipate heat and not the circuit board.
  • To fully realize the heat dissipating potential of low thermal coefficient packages with large tabs or bottom side thermal pads, you have to place several thermal vias in the pad to tie this pad to the internal ground plane or a large copper pour on the back of the PCB. You also need to pay special attention to the datasheet on parts with an exposed bottom side pad. These exposed pads are often connected to ground internally but not always and on some parts the pad may be the only ground connection for the part. On other parts, the pad may not be electrically connected and can be safely grounded or it may be the negative voltage supply on dual supply analog parts (which may or may not be ground in your design). The datasheets usually contain details on the size of the copper area and other PCB layout requirements to achieve the specified thermal resistances. The diagram below shows a typical arrangement for a DPAK and SMT DIP packages with a thermal copper pour and vias to connect to an internal ground plane or back-side copper pour. Most of the IC manufacturers that have packages with bottom side thermal pads provide app notes or even on-line calculators to help determine the minimum size of the copper area and number of thermal vias you need for a given package.

Footprints with Cu pour

  • With thermal vias, more isn’t always better since they can also disrupt the spread of heat across a copper pour or ground plane. The ground plane connections for vias are usually made with four thermal “spokes” and not a direct connection, some of these spokes may be missing if the vis are packed too close together. Some assembly houses may complain about thermal vias in device pads robbing solder from the pad. If so, reducing the via size or covering the via on the opposite side of the board with solder mask can help minimize the amount of solder that may seep into the via holes.
  • When using the PCB for heat sinking, keep in mind that FR4 and other laminates that PCBs are commonly made from are very poor thermal conductors. You are really spreading the heat through the copper in/on the PCB instead of transferring the heat into the PCB. It is best to use at least 2 oz copper for the outer layers and 1oz copper for inner layers. The heavier copper isn’t significantly more expensive than the “standard” 1 oz and ½ oz copper used for most PCBs but does provide significantly better heat transfer across the ground plane and copper pours.
  •  If you have traces on your board that carry more than a few amps, the traces themselves can be a significant source of heat if you aren’t careful. There are a number of good on-line PCB trace width calculators you can use to help prevent this. The maximum allowed temperature increase for the trace is an input for most of these calculators. If a trace normally carries high current you should set this to 5°C or 10°C. If the high currents are of a fairly low frequency and short duration, you can usually go as high as 25°C max temperature rise (but first make certain your product isn’t subject to any specifications that restrict the max temperature rise of traces). The overall trace resistance is also a function of trace length so you can reduce this resistance and resulting generated heat by shortening the trace length. Vias can have significantly higher resistance than copper traces causing them to generate additional heat so above a few amps you should use multiple vias instead of a single via.
  • To some degree the leakage current of an IC is influenced by the die size and circuit density on the die. For typical embedded devices the micro will usually have the largest die size and highest circuit density of the ICs in the device and therefore the highest leakage current. Simply increasing the space between heat generating parts and the micro can drastically reduce the amount of heat the micro is exposed to thereby decreasing its leakage current.
  • If possible, heat sink your heat generating parts to the enclosure. You may be able to do this directly but also indirectly be placing your heat generating parts near mounting holes on the board so the mounting hardware can help carry the heat out of the circuit board.
  • Pay the premium for more efficient voltage regulators. The power that an inefficient regulator wastes is generally turned into heat which can increase the power consumed. You aren’t likely to get into a thermal runaway condition but to some degree this increased power consumption generates more heat which increases power consumption which generates more heat …. you get the point.

That wraps up this part on thermal management. As you can tell while much of thermal management is in the circuit board layout, the extent that heat can be managed in the layout and the impact heat will have on the power consumption of your design are highly dependent on device and part package selection.

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Leakage current & current leaks – part 2

Virtually all semiconductor devices have some amount of leakage current. It is interesting to note as operating voltages and device power consumption keep dropping, leakage current is becoming a larger percentage of a device’s power consumption. In most cases there isn’t much you can do about leakage currents other than be aware of them and account for them in your power analysis. In some cases there may be a significant difference in leakage current levels from manufacturer to manufacturer for devices that perform the same function so it pays to take the time to include leakage current comparison in your component selection. For a CMOS device that isn’t actively being clocked, leakage current can make up a significant part of its power consumption that may be called out as “standby current” or “quiescent state current” in the datasheet specs.

Diodes (including LEDs) are one a few types of devices where the circuit design can play a part in determining the extent of the leakage current in that design.

Diode & LED leakage current

Diodes can present substantial leakage currents when in a reverse voltage condition, this is often referred to as reverse current. Similar to capacitors, there are a number of factors that come into play in determining the level of leakage current. Unlike capacitors, there aren’t any simple formulas to help you estimate what the reverse current is for a diode. Diode reverse current varies considerably from device to device and isn’t necessarily dependent on voltage rating, current rating or physical size.

The graph below shows a typical diode voltage/current curve. Notice that under forward voltage conditions (blue shaded area) diodes conduct very little current until the voltage starts approaching the diode’s forward voltage. Although not technically a leakage current, current will start flowing at a few hundred millivolts below the forward voltage level where the diode is expected to “turn on” and start conducting. Under reverse voltage conditions (pink shaded area), some amount of leakage current occurs as soon as the voltage is reversed and increases as the reverse voltage increases. Note that this graph is not to scale, the forward voltage of a diode is typically less than one volt while the reverse voltage and breakdown voltage are usually tens to hundreds of volts.

diode V-C curve

There are a few things to consider regarding diode reverse current:

  • Schottky diodes tend to have higher reverse currents than standard diodes.  In a recent search on DigiKey, for SMT Schottky diodes the reverse current specs ranged from 100nA to 15mA while for standard diodes the range was nearly an order of magnitude lower, from 500pA to 1.5mA. A Schottky diode may be appropriate for your design because of its low forward voltage but be aware that its leakage current can be considerable.
  • Similar to leakage current for caps, the applied voltage relative to the rated reverse voltage can have a significant impact on the reverse current of diodes. Reductions in reverse current as the applied voltage is reduced relative to the rated reverse voltage aren’t quite linear but can reach 90% or more.  This is often shown in a graph in the diode data sheet with reverse current plotted against percent of rated reverse voltage.
  • Temperature will also have a significant impact on a diode’s reverse current.  It is not uncommon for a 20°C temperature increase to cause a 10X or greater increase in reverse current. One option to improve this situation in power application where a diode can heat up while operating is to utilize a physically larger device and large copper areas on the circuit board to help transfer heat out of the diode and into the circuit board.
  • As shown above, the reverse current can become significant as the breakdown voltage is approached and increase to many times the rated current of the device if the breakdown voltage is exceeded. This is referred to as “avalanche current” because of the sudden increase and is the point where the part is likely to be destroyed.

LEDs will exhibit similar reverse and forward currents as other diodes. A few things to consider specific to how LEDs are typically used:

  • Reverse voltage with an LED typically is not a problem unless there are multiple power rails in a design and the cathode is driven to a higher voltage than the anode when the LED is off.
  • It can be tempting to use a high-drive GPIO to directly control an LED as shown in the diagram below. Because of the typical logic “high” and “low” levels of a CMOS micro, this can still result in hundreds of millivolts across the LED when it is off. This will create the condition just to the left of the “Forward Voltage” point on the voltage/current curve where there may be from tens of microamps to a few milliamps of current flow through the LED. If you choose to use a GPIO for cost/space reasons, it is better to connect the GPIO to the anode side and drive it high to turn on the LED. A CMOS micro will usually have a low level output below 0.4V while the high level can be as low as 70% of the Vcc rail. If you connect the GPIO to the cathode, at 70% of 3.3V that is only 2.3V which may not even be high enough to turn the LED completely off.
  • To virtually eliminate the current flow through an LED in the off state, use an N-channel MOSFET to control the cathode of the LED (see diagram below). This allows the cathode to float so the only current paths available are the circuit board itself and the solder mask (typically 100M ohm or higher) and the leakage current path through the MOSFET (typically in the low nanoamp range for a small N-channel FET but it can vary).

LED hookups

Unrelated to leakage current, LEDs can waste a lot of power if used without careful consideration.  Users love LED indicators but generally don’t have a clue about their impact on a device’s battery life. When LEDs are required, here are a few things to consider to reduce their power consumption:

  • Keep in mind that with current requirements of minimally several milliamps, an LED can draw much more current than a sleeping or slow running micro and high brightness LEDs can draw more current than a Bluetooth or ZigBee radio uses when transmitting.
  • Think about how bright your LEDs really need to be. Really bright LEDs generally aren’t needed unless a device is used outdoors or needs to be visible from across a large room. Light pipes and similar low cost plastic optics can be very useful for making an LED appear to be brighter or larger and may allow you to decrease the LED current by several milliamps. Particularly in red and green, high efficiency LEDS are available today that provide much better brightness/power performance than older LEDs.
  • When using an LED as an on/off indicator, consider a slow flash of the LED instead of having it on constantly.  Turning the LED on for ½ second every 3 seconds provides an almost 84% reduction in the power used for this indicator.
  • On a much smaller time scale, use a PWM to control the on/off duty cycle of the LED. LEDs tend to stay lit for a relatively long time after they are turned off. Switching the LED on/off with a 50/50 duty cycle at a rate faster than 1Khz will cut the power by half with an imperceptible reduction in brightness. The timers on many modern micros have PWM outputs or other output modes that can be used for this with little to no involvement by the firmware other than starting or stopping the timer.
  • If your device has more than a few LEDs that can be on simultaneously, consider adding an ambient light sensor to your product and controlling a PWM to adjust the brightness based on ambient light conditions.

Up to this point I have covered leakage currents, currents that may not be obvious but are usually specified in part data sheets. This part will deal with “current leaks”, non-obvious current flows and power losses that are caused by the circuit design. In some cases these “current leaks” may be reduced or managed somehow, in other cases you just need to be aware of them so they can be accounted for in your power budget.

Before leaving semiconductor devices, one of the biggest power wasters if not used carefully are MOSFETs. While MOSFETs usually have a leakage current spec, it is usually on the order of tens to a few hundred nanoamps. The bigger issue with MOSFETs is inefficient operation from not operating them under the right conditions to allow them to meet their Rds(on) spec. Borrowed from the “Low Power Design” e-book, here are a few things to consider when using MOSFETs:

  • The efficiency of a MOSFET is a function of gate voltage and load current. Most N-channel FETs usually need a gate voltage in the 8-10V range to fully turn on so simply driving the gate with a GPIO won’t put the FET in its lowest RDS(on) range. Logic level gate FETs may be better in this regard but typically they just have a lower minimum turn-on threshold and may still need over 5V to achieve their RDS(on) spec. In these cases you should consider using a P-channel FET or even a gate driver IC to drive the gate of the N-channel FET with the voltage it is switching (or use a step-up regulator or voltage doubler circuit to provide a higher voltage if the input voltage exceeds the maximum gate voltage). The graph below shows the impact of gate voltage on Rds(on) for the Fairchild FDS8449 N-channel FET. The FDS8449 has a max gate turn-on threshold of 3V but as you can see at 3V the Rds(on) is about 2.4X higher than at 10V at no load, much higher as the load increases.

Rds(on) vs gate voltage

  • When using a P-channel FET to drive a load, a GPIO may not drive the gate high enough to completely turn off the FET so you may be leaking power through the FET. This can often go un-noticed since the amount of power is too low to activate the load.
  • A P-channel FET of similar rated voltage and current as an N-channel FET will typically have 50-100% higher Rds(on) than the N-channel FET. With Rds(on) specs on modern FETs in the double-digit milliohm range even doubling the Rds(on) produces a fairly low value. However, that is simply wasted power that can easily be eliminated if low-side switching is an option for your application. This is also important to keep in mind if for some reason you can’t address one of the issues discussed here that prevents the FET from operating close to its lowest Rds(on), changing the type of FET may alleviate the problem. If you have a P-channel FET operating at 2X its lowest Rds(on) then you could possibly reduce the Rds(on) by a factor of 4X by using an N-channel FET.
  • Just like a resistor, the Rds(on) of a FET increases with temperature. The graph below shows the impact of temperature on Rds(on) for the Fairchild FDS8449 N-channel FET. As you can see, a 50°C increase in temperature results in a nearly 20% increase in Rds(on). Even if your product is normally used in a room temperature environment, a 20-50°C temperature rise at the FET’s die isn’t uncommon (another reason to operate the FET in its lowest Rds(on) range). This is another situation where keeping a part cooler helps prevent wasting power, as the Rds(on) increases the part will get hotter, increasing the Rds(on) and so on. Thermal runaway isn’t likely to happen but a hot FET and a non-optimal gate voltage can combine to generate a lot of excess heat and waste a lot of power.

Rds(on) vs junct temp

This started out to be a 2 part article, next week I’ll cover more sources of power loss commonly found in circuit designs to wrap-up the 3rd and final part.